Filter
Top Products
Intel® PXA26x Processor Family Developer’s Manual 14-7
Inter-Integrated Circuit Sound Controller
Figure 14-1 and Figure 14-2 provide timing diagrams that show formats for I
2
S and MSB-justified
modes of operations.
Data is transmitted and received in frames of 64 BITCLK cycles. Each frame consists of a Left
sample and a Right sample. Each sample holds 16-bit of valid data. The LSB 16-bit of each sample
is padded with zeros.
In the Normal I
2
S mode, the SYNC is low for the Left sample and high for the Right sample. Also,
the MSB of each data sample lags behind the SYNC edges by one BITCLK cycle.
In the MSB-Justified mode, the SYNC is high for the Left sample and low for the Right sample.
Also, the MSB of each data sample is aligned with the SYNC edges.
14.6 I
2
S Controller Register Descriptions
The I
2
S controller registers are all 32-bit addressable, ranging from 0x4040-0000 through 0x404F-
FFFF.
The I
2
S Controller has the following types of registers:
• Control registers are used to program common control, alternate mode specific control.
• The Data Register is used for transmit and receive fifo accesses.
Figure 14-1. I
2
S Data Formats (16 bits)
Figure 14-2. MSB-Justified Data Formats (16 bits)
A8842-01
SYNC
BITCLK
Note: Timing for SData_In is identical to SData_Out.
SData_Out
cycle0
Left Right
012
15 14 13 3 2 1 0
15 14 13 12 3 2 1 0
3 13 141516 293031 323334 35 45464748 6263 0
A8843-01
SYNC
BITCLK
Note: Timing for SData_In is identical to SData_Out.
SData_Out
cycle0
Left Right
012
15 14 13 3 2 1 0
15 14 13 12 3 2 1 0
3 13 141516 293031 323334 35 45464748 6263 0