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Intel® PXA26x Processor Family Developer’s Manual 15-11
MultiMediaCard Controller
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of two
more bytes and 8-, 16- or 32-byte bursts and program the descriptor to set an interrupt, for the
software to write the MMC_PRTBUF[BUF_PART_FULL] bit.
• Transmit 105 bytes:
Write 32 bytes three times, then write nine more bytes.
For the DMA, use three descriptors of 32 bytes and 32-byte bursts and one descriptor of nine
more bytes and 16- or 32-byte bursts and program the descriptor to set an interrupt, for the
software to write MMC_PRTBUF[BUF_PART_FULL] bit.
15.2.8.4 DMA and Program I/O
The software may communicate to the MMC controller via the DMA or program I/O.
To access the FIFOs with the DMA, the software must program the DMA to read or write the
MMC FIFOs with single byte transfers, and 32-byte bursts. For example, to write 64 bytes of data
to the MMC_TXFIFO, the software must program the DMA to write 64 bytes with an 8-bit port
size to the MMC and for 32-byte bursts. The MMC issues a request to read the MMC_RXFIFO and
a request to write the MMC_TXFIFO.
With program I/O, the software waits for the MMC_I_REG[RXFIFO_RD_REQ] or
MMC_I_REG[TXFIFO_WR_REQ] interrupts before reading or writing the respective FIFO.
The CMDAT[DMA_EN] bit must be set to a 1 to enable communication with the DMA and it must
be set to a 0 to enable program I/O.
15.3 Card Communication Protocol
This section discusses the software’s responsibilities and the communication protocols used
between the MMC and the card.
15.3.1 Basic, No Data, Command and Response Sequence
The MMC controller performs the basic MMC or SPI bus transaction. It formats the command
from the command registers and generates and appends the 7-bit CRC if applicable. It then serially
translates this to the MMCMD bus, collects the response data, and validates the response CRC. It
also checks for response time-outs and card busy if applicable. The response data is in the
MMC_RES FIFO and the status of the transaction is in the status register, MMC_STAT.
The protocol of events for the software is:
1. Stop the clock
2. Write 0x6f to the MMC_I_MASK register and wait for and verify the
MMC_I_REG[CLK_IS_OFF] interrupt
3. Write to the following registers, as necessary:
— MMC_CMD
— MMC_ARGH
— MMC_ARGL
— MMC_CMDAT, this register must be written, even if there is no change to the register