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6-20 Intel® PXA26x Processor Family Developer’s Manual
Memory Controller
1x13x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 ‘0’ 8 7 6 5 4 3 2 1
1x13x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 ‘0’ 10 9 8 7 6 5 4 3 2
1x13x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 ‘0’ 9 8 7 6 5 4 3 2 1
1x13x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x13x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 ‘0’ 10 9 8 7 6 5 4 3 2 1
1x13x11x32 13 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ‘0’ 11 10 9 8 7 6 5 4 3 2
1x13x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 11 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x11x8x32 22212019181716151413121110 2221‘0’ 9 8 7 6 5 4 3 2
2x11x8x16 212019181716151413121110 9 2120‘0’ 8 7 6 5 4 3 2 1
2x11x9x32 23222120191817161514131211 2322‘0’ 10 9 8 7 6 5 4 3 2
2x11x9x16 22212019181716151413121110 2221‘0’ 9 8 7 6 5 4 3 2 1
2x11x10x32 24 23 22 21 20 19 18 17 16 15 14 13 12 24 23 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x11x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 22 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x11x11x32 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x11x11x16 NOT VALID (illegal addressing combination) NOT VALID (illegal addressing combination)
2x12x8x32 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2
2x12x8x16 22 21 20 19 18 17 16 15 14 13 12 11 10 9 22 21 ‘0’ 8 7 6 5 4 3 2 1
2x12x9x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 ‘0’ 10 9 8 7 6 5 4 3 2
2x12x9x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 23 22 ‘0’ 9 8 7 6 5 4 3 2 1
2x12x10x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x12x10x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 24 23 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x12x11x32 26 25 24 23 22 21 20 19 18 17 16 15 14 13 26 25 12 ‘0’ 11 10 9 8 7 6 5 4 3 2
2x12x11x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 25 24 11 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 ‘0’ 9 8 7 6 5 4 3 2
2x13x8x16 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 23 22 ‘0’ 8 7 6 5 4 3 2 1
2x13x9x32 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 ‘0’ 10 9 8 7 6 5 4 3 2
2x13x9x16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 ‘0’ 9 8 7 6 5 4 3 2 1
2x13x10x32 NOT VALID (too big) NOT VALID (too big)
2x13x10x16 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 25 24 ‘0’ 10 9 8 7 6 5 4 3 2 1
2x13x11x32 NOT VALID (too big) NOT VALID (too big)
2x13x11x16 NOT VALID (too big) NOT VALID (too big)
Table 6-8. External to Internal Address Mapping for Normal Bank Addressing (Sheet 2 of 2)
# Bits
Bank x
Row x
Col x
Data
External Address pins at SDRAM RAS Time
MA<24:10>
External Address pins at SDRAM CAS Time
MA<24:10>
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10