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12-14 Intel® PXA26x Processor Family Developer’s Manual
Universal Serial Bus Device Controller
16. Software clears the UDC interrupt bit and returns from the interrupt service routine.
If the host sends another SETUP command during these steps, the software must terminate the first
SETUP command and start the new command.
12.5.3 Case 3: EP0 Control Write With or Without a Premature
Status Stage
1. When software starts, it initializes a software state machine to EP0_IDLE. The software state
machine is used to track stages when software communicates with the host PC.
2. The host PC sends a SETUP command.
3. UDC generates an EP0 Interrupt.
4. Software determines that the UDCCS0[SA] and UDCCS0[OPR] bits are set. This indicates
that a new OUT packet is in the EP0 Buffer and identifies a SETUP transaction.
5. Software reads the data into a buffer while UDCCS0[RNE] bit (receiver not empty) is set.
6. Software parses the command in the buffer and determines that it is a Control Write (such as
Set Descriptor).
7. Software sets the internal to EP0_OUT_DATA_PHASE and clears the UDCCS0[OPR] and
UDCCS0[SA] bits.
8. To allow a premature STATUS IN stage, software sets the UDCCS0[IPR] bit and loads a zero-
length packet in the transmit FIFO.
9. Software clears the UDC interrupt bit and returns from the interrupt service routine.
10. The host PC issues an OUT packet and the UDC issues an EP0 interrupt.
11. Software enters the ISR routine and determines that it is in the EP0_OUT_DATA_PHASE
state, the UDCCS0[OPR] bit is set, and the UDCCS0[SA] bit is clear. This indicates that there
is more data to receive.
12. Software reads the data into a buffer while UDCCS0[RNE] bit is set and clears the
UDDCCS0[OPR] bit.
13. Software sets the UDCCS0[IPR] bit to allow a premature STATUS IN stage.
14. Software clears the UDC interrupt bit and returns from the interrupt service routine.
15. Steps 11 through 14 are repeated until all of the data is received.
16. As Steps 11 through 14 are repeated, the host sends a STATUS IN stage, which indicates that
the host PC can not send more data, instead of an OUT packet. The STATUS IN stage may be
premature or not.
17. Because software loaded a zero-length packet (see Step 8), the UDC responds to the STATUS
IN by sending a a zero-length packet back to the host PC. This causes an interrupt.
18. Software enters the ISR routine and determines that it is in the EP0_OUT_DATA_PHASE
state and the UDCCS0[OPR] and UDCCS0[IPR] bits are clear. This indicates that a STATUS
IN stage occurred.
19. Software determines how many bytes were received before the interrupt and compares the
number of received bytes to the wLength field in the original SETUP packet. If the correct
amount of data was sent, software parses the data and performs the action the data indicates. If