Filter
Top Products
viii Intel® PXA26x Processor Family Developer’s Manual
Contents
9.3.2 Inter-Integrated Circuit Bus Interface Modes.......................................................9-3
9.3.3 Start and Stop Bus States ....................................................................................9-4
9.4 Inter-Integrated Circuit Bus Operation...............................................................................9-6
9.4.1 Serial Clock Line (SCL) Generation......................................................................9-7
9.4.2 Data and Addressing Management ......................................................................9-7
9.4.3 Inter-Integrated Circuit Acknowledge....................................................................9-8
9.4.4 Arbitration .............................................................................................................9-9
9.4.5 Master Operations ..............................................................................................9-11
9.4.6 Slave Operations ................................................................................................9-15
9.4.7 General Call Address..........................................................................................9-16
9.5 Slave Mode Programming Examples ..............................................................................9-18
9.5.1 Initialize Unit .......................................................................................................9-18
9.5.2 Write n Bytes as a Slave.....................................................................................9-18
9.5.3 Read n Bytes as a Slave ....................................................................................9-19
9.6 Master Programming Examples ......................................................................................9-19
9.6.1 Initialize Unit .......................................................................................................9-19
9.6.2 Write 1 Byte as a Master ....................................................................................9-19
9.6.3 Read 1 Byte as a Master ....................................................................................9-20
9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9-20
9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort ..................................9-21
9.7 Glitch Suppression Logic.................................................................................................9-22
9.8 Reset Conditions .............................................................................................................9-22
9.9 Register Definitions..........................................................................................................9-22
9.9.1 I2C Bus Monitor Register- IBMR ........................................................................9-22
9.9.2 I2C Data Buffer Register- IDBR..........................................................................9-23
9.9.3 I2C Control Register- ICR...................................................................................9-24
9.9.4 I2C Status Register.............................................................................................9-26
9.9.5 I2C Slave Address Register- ISAR.....................................................................9-28
10 Universal Asynchronous Receiver/Transmitter ..........................................................................10-1
10.1 Feature List......................................................................................................................10-1
10.2 Overview..........................................................................................................................10-2
10.2.1 Full Function UART ............................................................................................10-2
10.2.2 Bluetooth UART..................................................................................................10-2
10.2.3 Standard UART ..................................................................................................10-2
10.2.4 Compatibility with 16550.....................................................................................10-2
10.3 Signal Descriptions..........................................................................................................10-3
10.4 UART Operational Description ........................................................................................10-4
10.4.1 Reset ..................................................................................................................10-5
10.4.2 Internal Register Descriptions.............................................................................10-5
10.4.3 FIFO Interrupt Mode Operation ........................................................................10-21
10.4.4 FIFO Polled Mode Operation............................................................................10-22
10.4.5 DMA Requests..................................................................................................10-22
10.4.6 Slow Infrared Asynchronous Interface..............................................................10-23
10.5 Register Summary.........................................................................................................10-26
10.5.1 UART Register Differences ..............................................................................10-27
11 Fast Infrared Communication Port..............................................................................................11-1
11.1 Signal Description............................................................................................................11-1
11.2 Fast Infrared Communications Port Operation ................................................................11-1