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2-18 Intel® PXA26x Processor Family Developer’s Manual
System Architecture
Miscellaneous Pins
BOOT_SEL
[2:0]
IC
BOOT SELECT PINS (input):
Indicates type of boot device. See Section 18.1,
“Initialization” for information on configuring BOOT_SEL
for proper flash initialization.
Input Input
PWR_EN OC
POWER ENABLE FOR THE POWER SUPPLY (output):
When negated, it signals the power supply to remove
power to the core because the system is entering sleep
mode.
Driven High
Driven low while
entering sleep
mode. Driven high
when sleep exit
sequence begins.
nBATT_FAULT IC
MAIN BATTERY FAULT (input):
Signals that main battery is low or removed. Assertion
causes PXA26x processor family to enter sleep mode or
force an imprecise data exception, which cannot be
masked. PXA26x processor family will not recognize a
wake-up event while this signal is asserted. Minimum
assertion time for nBATT_FAULT is 1 ms.
Input Input
nVDD_FAULT IC
VDD FAULT (input):
Signals that the main power source is going out of
regulation. nVDD_FAULT causes the PXA26x processor
family to enter sleep mode or force an Imprecise Data
Exception, which cannot be masked. nVDD_FAULT is
ignored after a wake-up event until the power supply timer
completes (approximately 10 ms). Minimum assertion time
for nVDD_FAULT is 1 ms.
Input Input
nRESET IC
HARD RESET (input):
Level sensitive input used to start the processor from a
known address. Assertion causes the current instruction to
terminate abnormally and causes a reset. When nRESET
is driven high, the processor starts execution from address
0. nRESET must remain low until the power supply is
stable.
Input
Input. Driving low
during sleep will
cause normal reset
sequence and exit
from sleep mode.
nRESET_OUT OC
RESET OUT (output):
Asserted when nRESET is asserted and deasserts after
nRESET is deasserted but before the first instruction
fetch. nRESET_OUT is also asserted for “soft” reset
events: sleep, watchdog reset, or GPIO reset.
Driven low during
any reset sequence –
driven high prior to
first fetch.
Driven Low
JTAG and Test Pins
nTRST IC
JTAG TEST INTERFACE RESET:
Resets the JTAG/Debug port. If JTAG/Debug is used,
drive nTRST from low to high either before or at the same
time as nRESET. If JTAG is not used, nTRST must be
either tied to nRESET or tied low.
Input Input
TDI IC
JTAG TEST DATA INPUT (input):
Data from the JTAG controller is sent to the PXA26x
processor family using this pin. This pin has an internal
pull-up resistor.
Input Input
TDO OCZ
JTAG TEST DATA OUTPUT (output):
Data from the PXA26x processor family is returned to the
JTAG controller using this pin.
Hi-Z Hi-Z
Table 2-6. Pin & Signal Descriptions for the PXA26x Processor Family (Sheet 10 of 12)
Pin Name Type Signal Descriptions Reset State Sleep State