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Interrupts
5-27
Program Control
Bit 0 MINT2 — Interrupt 2 mask. This bit masks the external interrupt INT2 or, in conjunc-
tion with the INT2/INT3 bit of the IMR, unmasks INT2
.
MINT2 = 0 INT2
is masked. Neither FINT2 nor bit 1 of the IFR (INT2/INT3) is set
by a request on the INT2
pin.
MINT2 = 1 INT3
is unmasked. Flag bits FINT2 and INT2/INT3 are both set by a
request on the INT2
pin.
5.6.7 Nonmaskable Interrupts
Hardware nonmaskable interrupts
can be requested through two pins:
RS (reset). RS is an interrupt that stops program flow, returns the proces-
sor to a predetermined state, and then begins program execution at ad-
dress 0000h. For details of the reset operation, see Section 5.7,
Reset Op-
eration
, on page 5-33. When RS is acknowledged, the interrupt mode
(INTM) bit of status register ST1 is set to 1 to disable maskable interrupts.
NMI. When NMI is activated (either by the NMI pin or by the NMI instruc-
tion), the processor switches program control to vector location 24h. In
addition, maskable interrupts are disabled (the INTM bit of status register
ST0 is set to 1). Although NMI
uses the same logic as the maskable inter-
rupts, it is not maskable. NMI
happens regardless of the value of the INTM
bit, and no mask bit exists for NMI
. If the NMI pin is not used, it should be
pulled high to prevent an accidental interrupt.
NMI can be used as a soft reset. Unlike a hardware reset (RS), the NMI
neither affects any of the modes of the device nor aborts a currently active
instruction or memory operation.
Software interrupts
(which are inherently nonmaskable) are requested by the
following instructions:
INTR. This instruction allows you to initiate any ’C2xx interrupt, including
user-defined interrupts INT8 through INT16 and INT20 through INT31.
The instruction operand (K) indicates which interrupt vector location the
CPU will branch to. To determine the operand K that corresponds to each
interrupt vector location see subsection 5.6.2 (on page 5-16). When an
INTR interrupt is acknowledged, the interrupt mode (INTM) bit of status
register ST1 is set to 1 to disable maskable interrupts.