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’C2xx Bus Structure
2-4
Figure 2–2. Bus Structure Block Diagram
B0
DARAM
ROM/
flash
SARAM
B1, B2
DARAM
Memory
mapped
registers
PAB
DRAB
DWAB
PRDB
DRDB
DWEB
Control bus
External
signals
Memory
control
MULTI_DSP
CLOCK/PLL
Interrupts
JTAG/TEST
Central processing unit (CPU)
Auxiliary
registers
registers
Status
ARAU
CALU
Accumulator
Multiplier
Product
shifter
Input
shifter
PREG
TREG
Output
shifter
External
address bus
External
data bus
Synchronous
serial port
Timer
Wait-state
generator
UART
On-chip peripherals/
registers mapped to
I/O space
Other I/O-mapped
registers