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Index-5
bus request pin (BR
)
definition 4-3
shown in figure 4-13, 4-15
buses
block diagram 2-4
data read bus (DRDB) 2-3
data write bus (DWEB) 2-3
data-read address bus (DRAB) 2-3
data-write address bus (DWAB) 2-3
program address bus (PAB)
definition 2-3
used in program-memory address genera-
tion 5-3
program read bus (PRDB) 2-3
C
C (carry bit)
affected during SFL and SFR instruc-
tions 7-157 to 7-159
definition 3-16
involved in accumulator events 3-10
used during ROL and ROR instruc-
tions 7-144 to 7-146
’C209 device 11-1 to 11-18
comparison to other ’C2xx devices 11-2
differences in interrupts 11-3
differences in memory and I/O spaces 11-3
differences in peripherals 11-2
similarities 11-2
interrupts 11-10
locating ’C209 information in this manual
(table) 11-3
memory and I/O spaces 11-5
on-chip peripherals 11-14
cable, target system to emulator E-1 to E-25
cable pod E-5, E-6
CAD bit 10-8
CALA instruction 7-58
CALL instruction 7-59
call instructions
call subroutine at location specified by accumula-
tor (CALA) 7-58
call subroutine conditionally (CC) 7-60
call subroutine unconditionally (CALL) 7-59
conditional, overview 5-12
unconditional, overview 5-8
CALU (central arithmetic logic unit)
definition F-4
description 3-9
carry bit (C)
affected during SFL and SFR instruc-
tions 7-157 to 7-159
definition 3-16
involved in accumulator events 3-10
used during ROL and ROR instruc-
tions 7-144 to 7-146
CC instruction 7-60
central arithmetic logic section of CPU 3-8
central arithmetic logic unit (CALU).
See
CALU
central processing unit.
See
CPU
CIO0–CIO3 (bits), configuring pins IO0–IO3 as in-
puts/outputs 10-15
CLK register
description 8-7
quick reference A-11
reset condition 5-34
CLKIN signal 8-4 to 8-6
CLKMOD pin 11-14, F-4
CLKOUT1 bit 8-7
CLKOUT1 signal 8-4 to 8-6
definition F-4
turning CLKOUT1 pin on and off 8-7
CLKOUT1-pin control (CLK) register
description 8-7
quick reference A-11
reset condition 5-34
CLKR pin
as bit input (IN0 bit) 9-10
definition 9-4
CLKX pin 9-4
clock generator 8-4 to 8-6
’C209 clock options 11-14 to 11-18
introduction 2-11
modes
’C203/C204 8-5
’C209 11-14 to 11-18
clock mode bit (MCM) 9-11
clock modes
clock generator
’C203/C204 8-5
’C209 11-14
synchronous serial port 9-11
CLRC instruction 7-62
CMPL instruction 7-64