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Index-13
L
LACC instruction 7-72
LACL instruction 7-75
LACT instruction 7-78
LAR instruction 7-80
latch phase of CPU cycle F-13
latency, interrupt 5-30 to 5-36
after execution of RET 5-32
during execution of CLRC INTM 5-31
minimum latency 5-30
LDP instruction 7-83
local data memory
address map
’C203 4-32
’C204 4-35
’C209 11-6
configuration
RAM (dual-access)
’C203 4-33
’C204 4-36
’C209 11-8
RAM (single-access) 11-7
description 4-7
external interfacing 4-9
caution about proper timing 4-9
pages of (diagram) 4-7
logic instructions
AND 7-34
CMPL (complement/NOT) 7-64
OR 7-129
XOR (exclusive OR) 7-193
logic phase of CPU cycle F-13
long immediate addressing 6-2
LPH instruction 7-85
LST instruction 7-87
LT instruction 7-91
LTA instruction 7-93
LTD instruction 7-95
LTP instruction 7-98
LTS instruction 7-100
M
MAC instruction 7-102
MACD instruction 7-106
MAR instruction 7-111
mask bits
asynchronous serial port control register
(ASPCR) 10-8
interrupt control register (ICR) 5-24
interrupt mask register (IMR) 5-22
maskable interrupts 5-18
acknowledgement conditions 5-19
definition 5-15
enabling/disabling with INTM bit 5-19
flag bits in ICR 5-24
flag bits in IFR 5-20
flow chart of operation 5-20
flow chart of requesting INT2
and INT3 5-18
masking/unmasking in ICR 5-24
masking/unmasking in IMR 5-22
MCM bit 9-11
memory
See also
I/O space
address map
’C203 4-32
’C204 4-35
’C209 11-6
data page 0 4-8
available on TMS320C2xx devices 2-7
available types 1-6
boot loader 4-14
boot source (EPROM) 4-14
diagram 4-14
enabling 4-17
execution 4-18
generating code for EPROM C-23 to C-24
program code 4-21
data page pointer (DP) 3-16
device-specific information 4-31
direct memory access (using HOLD opera-
tion) 4-27
during reset 4-29
example 4-28
terminating correctly 4-29
external interfacing
global data memory 4-12
I/O ports 4-25
local data memory 4-9
program memory 4-5
flash, introduction 2-9
global data memory 4-11 to 4-13
HOLD operation 4-27 to 4-30
during reset 4-29
example 4-28
terminating correctly 4-29