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Controlling and Resetting the Port
9-9
Synchronous Serial Port
Table 9–2. Run and Emulation Modes
FREE SOFT Run/Emulation Mode
0 0 Immediate stop
0 1 Stop after completion
of word
1 0 Free run
1 1 Free run
Note:
If an option besides immediate stop is chosen for the receiver, an overflow
error is possible. The default mode (selected at reset) is
immediate stop.
Bit 13 TCOMP — Transmission complete. This bit is cleared to 0 when all data
in the transmit FIFO buffer has been transmitted (the buffer is empty) and is
set to 1 when new data is written to the transmit FIFO buffer (the buffer is not
empty).
Bit 12 RFNE — Receive FIFO buffer not empty bit. This bit is 1 when the receive
FIFO buffer contains data and is cleared when the buffer empties.
Bits 11–10 FT1, FT0 — FIFO transmit-interrupt bits. The values you write to FT0 and
FT1 set an interrupt trigger condition based on the contents of the transmit
FIFO buffer. When this condition is met, a transmit interrupt (XINT) is gener-
ated and the data can be transferred out to the FIFO buffer using the OUT
instruction. Table 9–3 summarizes the possible trigger conditions.
Table 9–3. Controlling Transmit Interrupt Generation by Writing to Bits FT1 and FT0
Select Bits
FT1 FT0 Generate XINT when...
0 0 Transmit FIFO buffer can accept one or more words;
XINT occurs repeatedly until the buffer is full.
0 1 Transmit FIFO buffer can accept two or more words;
XINT occurs repeatedly until three words are written.
1 0 Transmit FIFO buffer can accept three or four words;
XINT occurs repeatedly until two words are written.
1 1 Transmit FIFO buffer is empty (can accept 4 words);
XINT occurs repeatedly until one word is written.