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F-21
Glossary
single-access RAM: See
SARAM
.
slave phase: See
latch phase
.
SOFT bit (asynchronous serial port): Bit 14 in the asynchronous serial
port control register (ASPCR); a special emulation bit that is used in con-
junction with bit 15 (FREE) to determine the state of an asynchronous
serial port transfer when a software breakpoint is encountered during
emulation. When FREE = 0, SOFT determines the emulation mode. See
also
FREE bit (asynchronous serial port)
.
SOFT bit (synchronous serial port): Bit 14 of the synchronous serial port
control register (SSPCR); a special emulation bit that is used in conjunc-
tion with bit 15 (FREE) to determine the state of a synchronous serial port
transfer when a software breakpoint is encountered during emulation.
When FREE = 0, SOFT determines the emulation mode. See also
FREE
bit (synchronous serial port)
.
SOFT bit (timer): Bit 10 of the timer control register (TCR); a special emula-
tion bit that is used in conjunction with bit 11 (FREE) to determine the
state of the timer when a software breakpoint is encountered during
emulation. When FREE = 0, SOFT determines the emulation mode.
SOFT and FREE are not available in the TCR of the ’C209. See also
FREE bit (timer)
.
software interrupt: An interrupt caused by the execution of an INTR, NMI,
or TRAP instruction.
software stack: A program control feature that allows you to extend the
hardware stack into data memory with the PSHD and POPD instructions.
The stack can be directly stored and recovered from data memory, one
word at time. This feature is useful for deep subroutine nesting or protec-
tion against stack overflow.
SSPCR:
Synchronous serial port control register.
A 16-bit I/O-mapped regis-
ter that you write to when setting the configuration of the synchronous
serial port and that you read when obtaining the status of the port.
ST0 and ST1: See
status registers ST0 and ST1
.
stack: A block of memory reserved for storing return addresses for subrou-
tines and interrupt service routines. The ’C2xx stack is 16 bits wide and
eight levels deep.
start bit: Every 8-bit data value transmitted or received by the asynchronous
serial port must be preceded by a start bit, a logic 0 pulse.
Glossary