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Controlling and Resetting the Port
10-12
Bit 7 DIO3 — Change detect bit for IO3. DIO3 indicates whether a change has
occurred on the IO3 pin. A change can be detected only when IO3 is config-
ured as an input by the CIO3 bit of the ASPCR (CIO3 = 0) and the serial port
is enabled by the URST bit of the ASPCR (URST = 1). Writing a 1 to DIO3
clears it to 0.
The detection of a change on the IO3 pin also generates an interrupt
(TXRXINT).
DIO3 = 0 No change is detected on IO3.
DIO3 = 1 A change is detected on IO3.
Bit 6 DIO2 — Change detect bit for IO2. DIO2 indicates whether a change has
occurred on the IO2 pin. A change can be detected only when IO2 is config-
ured as an input by the CIO2 bit of the ASPCR (CIO2 = 0) and the serial port
is enabled by the URST bit of the ASPCR (URST = 1). Writing a 1 to DIO2
clears it to 0.
The detection of a change on the IO2 pin also generates an interrupt
(TXRXINT).
DIO2 = 0 No change is detected on IO2.
DIO2 = 1 A change is detected on IO2.
Bit 5 DIO1 — Change detect bit for IO1. DIO1 indicates whether a change has
occurred on the IO1 pin. A change can be detected only when IO1 is config-
ured as an input by the CIO1 bit of the ASPCR (CIO1 = 0) and the serial port
is enabled by the URST bit of the ASPCR (URST = 1). Writing a 1 to DIO1
clears it to 0.
The detection of a change on the IO1 pin also generates an interrupt
(TXRXINT).
DIO1 = 0 No change is detected on IO1.
DIO1 = 1 A change is detected on IO1.
Bit 4 DIO0 — Change detect bit for IO0. DIO0 indicates whether a change has
occurred on the IO0 pin. A change can be detected only when IO0 is config-
ured as an input by the CIO0 bit of the ASPCR (CIO0 = 0) and the serial port
is enabled by the URST bit of the ASPCR (URST = 1). Writing a 1 to DIO0
clears it to 0.
The detection of a change on the IO0 pin also generates an interrupt
(TXRXINT).
DIO0 = 0 No change is detected on IO0.
DIO0 = 1 A change is detected on IO0.