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LAR
Load Auxiliary Register
7-82
Example 1 LAR AR0,16 ;(DP = 6: addresses 0300h–037Fh)
Before Instruction After Instruction
Data Memory Data Memory
310h 18h 310h 18h
AR0 6h AR0 18h
Example 2 LAR AR4,*–
Before Instruction After Instruction
ARP 4 ARP 4
Data Memory Data Memory
300h 32h 300h 32h
AR4 300h AR4 32h
Note:
LAR in the indirect addressing mode ignores any AR modifications if the AR
specified by the instruction is the same as that pointed to by the ARP. There-
fore, in Example 2, AR4 is not decremented after the LAR instruction.
Example 3 LAR AR4,#01h
Before Instruction After Instruction
AR4 0FF09h AR4 01h
Example 4 LAR AR6,#3FFFh
Before Instruction After Instruction
AR6 0h AR6 3FFFh