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I/O Space
4-26
Figure 4–13. I/O Port Interface Circuitry
A0
A1
A2
A3
D0
D1
D2
D3
D4
D5
D6
D7
IS
WE
1
2
3
6
4
5
18
16
14
12
9
7
5
3
3
4
7
8
13
14
17
18
11
1
5 V
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
15
14
13
12
11
10
9
7
2
4
6
8
11
13
15
17
1
19
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Input bit 0
Input bit 1
Input bit 2
Input bit 3
Input bit 4
Input bit 5
Input bit 6
Input bit 7
Output bit 0
Output bit 1
Output bit 2
Output bit 3
Output bit 4
Output bit 5
Output bit 6
Output bit 7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
D8
CLK
CLR
’C2xx DSP
74AC138
I/O port address decoder
74AC244
8-bit input port at
I/O address 0000h
5 V
74AC273
8-bit output latch
at I/O address 0001h