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Emulation Design Considerations
E-19
Design Considerations for Using XDS510 Emulator
Of the following two cases, the worst-case path delay is calculated to deter-
mine the maximum system test clock frequency.
Example E–3. Key Timing for a Single-Processor System Without Buffering (SPL)
t
pd TCK-DTMS
t
d DTMSmax
t
d DTCKHmin
t
su TTMS
t
TCKfactor
(
31 ns 2ns 10 ns
)
0.4
107.5 ns, or 9.3 MHz
t
pd TCK-DTDI
t
d TTDO
t
d DTCKLmax
t
su DTDLmin
t
TCKfactor
(
15 ns 16 ns 7ns
)
0.4
9.5 ns, or 10.5 MHz
In this case, the TCK-to-DTMS/DTDL path is the limiting factor.
Example E–4. Key Timing for a Single- or Multiprocessor-System With Buffered Input
and Output (SPL)
t
pd(TCK-TDMS)
t
d(DTMSmax)
t
DTCKHmin
t
su(TTMS)
t
(bufskew)
t
TCKfactor
(
31 ns 2ns 10 ns 1.35 ns
)
0.4
110.9 ns, or 9.0 MHz
t
pd(TCK–DTDI)
t
d(TTDO)
t
d DTCKLmax
t
su(DTDLmin)
t
d(bufskew)
t
TCKfactor
120 ns, or 8.3 MHz
(
15 ns 15 ns 7ns 10 ns
)
0.4
In this case, the TCK-to-DTDI path is the limiting factor.