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F-25
Glossary
URST:
Reset asynchronous serial port bit
. Bit 13 of the asynchronous serial
port control register (ASPCR); resets the asynchronous port.
V
vector: See
interrupt vector
.
vector location: See
interrupt vector location
.
W
wait state: A CLKOUT1 cycle during which the CPU waits when reading
from or writing to slower external memory.
wait-state generator: An on-chip peripheral that generates a limited num-
ber of wait states for a given off-chip memory space (program, data, or
I/O). Wait states are set in the wait-state generator control register
(WSGR).
WE
:
Write enable pin
. The ’C2xx asserts WE to request a write to external
program, data, or I/O space.
WSGR:
Wait-state generator control register.
This register, which is mapped
to I/O memory, controls the wait-state generator.
X
XF bit:
XF-pin status bit.
Bit 4 of status register ST1 that is used to read or
change the logic level on the XF pin.
XF pin:
External flag pin
. A general-purpose output pin whose status can be
read or changed by way of the XF bit in status register ST1.
XINT:
Transmit interrupt (synchronous serial port)
. An interrupt generated
during transmission based on the number of words in the transmit FIFO
buffer. The trigger condition (the desired number of words in the buffer)
is determined by the values of the transmit-interrupt bits (FT1 and FT0)
of the synchronous serial port control register (SSPCR).
XRST:
Transmit reset bit
. Bit 5 of the synchronous serial port control register
(SSPCR); resets the transmitter portion of the synchronous serial port.
XSR:
Transmit shift register.
Shifts data serially out of the synchronous serial
port through the DX pin. See also
RSR
.
GlossaryGlossary