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Controlling and Resetting the Port
9-13
Synchronous Serial Port
A transmit frame sync pulse marks the start of a data transmission. The syn-
chronous serial port can transmit using the internal frame sync source or using
an external source:
To use internal frame sync pulses, set the TXM bit in the SSPCR to 1.
To use external frame sync pulses:
1) Connect the frame sync source to the FSX pin of the transmitter and to
the FSR pin of the receiver.
2) Set the TXM bit in the SSPCR to 0 to enable external frame syncs.
The source configuration options are summarized in Table 9–5.
Table 9–5. Selecting Transmit Clock and Frame Sync Sources
MCM TXM CLKX source FSX source
0 0 External External
0 1 External Internal
1 0 Internal External
1 1 Internal Internal
9.3.3 Resetting the Synchronous Serial Port (Bits 4 and 5 of the SSPCR)
Reset the synchronous serial port by setting XRST = 0 and RRST = 0 and then
setting XRST = 1 and RRST = 1. These bits can be set individually, allowing
you to reset only the transmitter or only the receiver. When a zero is written to
one of these bits, activity in the corresponding section of the serial port stops.
9.3.4 Using Transmit and Receive Interrupts (Bits 8–11 of the SSPCR)
The synchronous serial port has two interrupts for managing reads and writes
to the FIFO buffers. The processor can determine when the FIFO buffers need
servicing in two ways:
By polling the SSPCR register (RFNE and TCOMP bits)
By setting up XINT and/or RINT interrupts
To determine when the FIFO buffers need servicing by polling, disable the in-
terrupts by masking them in the interrupt mask register (IMR).
If you want to use interrupts to manage your serial transfer, then perform three
steps: