Filter
Top Products
Clock Generator
8-6
Table 8–2. ’C2xx Input Clock Modes
Clock
Mode
CLKOUT1 Rate DIV2 DIV1
External
CLKIN Source?
Internal
Oscillator
Internal
PLL
÷ 2
CLKOUT1 = CLKIN ÷ 2
0 0 No Enabled Disabled
Yes Disabled Disabled
× 1 CLKOUT1 = CLKIN × 1 0 1 Required Disabled Enabled
× 2 CLKOUT1 = CLKIN × 2 1 0 Required Disabled Enabled
× 4 CLKOUT1 = CLKIN × 4 1 1 Required Disabled Enabled
Remember the following when configuring the clock mode:
The clock mode configuration cannot be dynamically changed. After you
change the levels on DIV1 and DIV2, the mode is not changed until a hard-
ware reset is executed (RS
low).
The operation of the PLL circuit is affected by the operating voltage of the
device. If your device operates at 5V, the PLL5V signal should be tied high
at the PLL5V pin. If you have a 3-V device, tie PLL5V low.
The ×1, ×2, and ×4 modes use an internal phase lock loop (PLL) that re-
quires approximately 2500 cycles to lock. Delay the rising edge of RS
until
at least three cycles after the PLL has stabilized. When the PLL is used,
the duty cycle of the CLKIN signal is more flexible, but the minimum duty
cycle should not be less than 10 nanoseconds. When the PLL is not used,
no phase-locking time is necessary, but the minimum pulse width must be
45% of the minimum clock cycle.