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Overview of the Memory and I/O Spaces
4-2
4.1 Overview of the Memory and I/O Spaces
The ’C2xx address map is organized into four individually selectable spaces:
Program memory (64K words) contains the instructions to be executed,
as well as data used during program execution.
Local data memory (64K words) holds data used by the instructions.
Global data memory (32K words) shares data with other processors or
serves as additional data space. Addresses in the upper 32K words
(8000h–FFFFh) of local data memory can be used for global data memory.
Input/output (I/O) space (64K words) interfaces to external peripherals
and contains registers for the on-chip peripherals.
These spaces provide a total address range of 224K words. The ’C2xx in-
cludes a considerable amount of on-chip memory to aid in system perfor-
mance and integration and a considerable amount of addresses that can be
used for external memory and I/O devices.
The advantages of operating from on-chip memory are:
Higher performance than external memory (because the wait states re-
quired for slower external memories are avoided)
Lower cost than external memory
Lower power consumption than external memory
The advantage of operating from external memory is the ability to access a
larger address space.
The ’C2xx design is based on an enhanced Harvard architecture. The ’C2xx
memory spaces are accessible on three parallel buses—the program address
bus (PAB), the data-read address bus (DRAB), and the data-write address bus
(DWAB). Because the operations of the three buses are independent, it is pos-
sible to access both the program and data spaces simultaneously. Within a
given machine cycle, the central arithmetic logic unit (CALU) can execute as
many as three concurrent memory operations.