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Register Descriptions
A-9
Register Summary
Timer Control Register (TCR) — Except ’C209 — I/O Address FFF8h
15 12 11 10 965 430
0 0 0 0 0 0 0
Reserved
†
FREE SOFT PSC TRB TSS TDDR
Start or restart timer.
Stop timer.
0
0
1
1
Stop after the next decrement of the TIM (hard stop).
Stop after the TIM decrements to 0 (soft stop).
Free run
Free run
Holds current prescale count for the timer
0
1
0
1
0
1
Emulation/run mode
Timer prescaler counter
Write 1 to reload timer counters.
Always read as 0
Timer reload bit
Timer stop status bit
Holds next value to be loaded into PSC
Timer divide-down register
R/WR/W
R/W R/W W R/W
†
These reserved bits are always read as 0s. Writes have no effect.
Timer Control Register (TCR) — ’C209 — I/O Address FFFCh
15 10 9–6 5 4 3–0
0 0 0 0 0
Reserved
†
PSC TRB TSS TDDR
R/W
Timer reload bit
Start or restart timer.
Stop timer.
0
1
Timer stop status bit
Holds next value to be loaded into the PSC
Timer divide-down register
Holds the current prescale count for the timer
Timer prescaler counter
Write 1 to reload timer counters. Always read as 0.
R/W W R/W
†
These reserved bits are always read as 0s. Writes have no effect.