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Glossary
receive interrupt (asynchronous serial port): An interrupt (TXRXINT)
caused during reception by any one of these events: the ADTR holds a
new character; overrun occurs; a framing error occurs; a break has been
detected on the RX pin; a character
A
or
a
has been detected in the ADTR
by the automatic baud-rate detection logic.
receive interrupt (synchronous serial port): See
RINT
.
receive interrupt mask bit (RIM): Bit 7 of the asynchronous serial port con-
trol register (ASPCR); enables or disables receive interrupts of the
asynchronous serial port.
receive pin (asynchronous serial port): See
RX pin
.
receive pin (synchronous serial port): See
DR pin
.
receive register (asynchronous serial port): See
ADTR
.
receive register (synchronous serial port): See
SDTR
.
receive reset (RRST) bit: Bit 4 of the synchronous serial port control regis-
ter (SSPCR); resets the receiver portion of the synchronous serial port.
receive shift register (asynchronous serial port): See
ARSR
.
receive shift register (synchronous serial port): See
RSR
.
repeat counter (RPTC): A 16-bit register that counts the number of times
a single instruction is repeated. RPTC is loaded by an RPT instruction.
reset: A way to bring the processor to a known state by setting the registers
and control bits to predetermined values and signaling execution to start
at address 0000h.
reset pin (RS
, also RS on ’C209): This pin causes a reset.
reset vector: The interrupt vector for reset.
return address: The address of the instruction to be executed when the
CPU returns from a subroutine or interrupt service routine.
RFNE bit:
Receive FIFO buffer not empty bit
. Bit 12 of the synchronous seri-
al port control register (SSPCR); indicates whether the receive FIFO
buffer of the synchronous serial port contains data to be read.
RIM bit: See
receive interrupt mask bit (RIM).
RINT:
Receive interrupt (synchronous serial port)
. An interrupt (RINT) gen-
erated during reception based on the number of words in the receive
FIFO buffer. The trigger condition (the desired number of words in the
buffer) is determined by the values of the receive-interrupt bits (FR1 and
FR0) of the synchronous serial port control register (SSPCR).
Glossary