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Multiplication Section
3-6
Inputs. The multiplier accepts two 16-bit inputs:
One input is always from the 16-bit temporary register (TREG). The TREG
is loaded before the multiplication with a data-value from the data read bus
(DRDB).
The other input is one of the following:
A data-memory value from the data read bus (DRDB).
A program memory value from the program read bus (PRDB).
Output. After the two 16-bit inputs are multiplied, the 32-bit result is stored in
the product register (PREG). The output of the PREG is connected to the 32-bit
product-scaling shifter. Through this shifter, the product may be transferred
from the PREG to the CALU or to data memory (by the SPH and SPL instruc-
tions).
3.2.2 Product-Scaling Shifter
The product-scaling shifter (product shifter) facilitates scaling of the product
register (PREG) value. The shifter has a 32-bit input connected to the output
of the PREG and a 32-bit output connected to the input of the CALU.
Input. The shifter has a 32-bit input connected to the output of the PREG.
Output. After the shifter completes the shift, all 32 bits of the result can be
passed to the CALU, or 16 bits of the result can be stored to data memory.
Shift Modes. This shifter uses one of four product shift modes, summarized
in Table 3–1. As shown in the table, these modes are determined by the prod-
uct shift mode (PM) bits of status register ST1. In the first shift mode (PM = 00),
the shifter does not shift the product at all before giving it to the CALU or to data
memory. The next two modes cause left shifts (of one or four), which are useful
for implementing fractional arithmetic or justifying products. The right-shift
mode shifts the product by six bits, enabling the execution of up to 128 consec-
utive multiply-and-accumulate operations without causing the accumulator to
overflow. Note that the content of the PREG remains unchanged; the value is
copied to the product shifter and shifted there.
Note:
The right shift in the product shifter is always sign extended, regardless of
the value of the sign-extension mode bit (SXM) of status register ST1.