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Instruction Set Summary
7-2
7.1 Instruction Set Summary
This section provides a summary of the instruction set in six tables (Table 7–1
to Table 7–6) according to the following functional headings:
Accumulator, arithmetic, and logic instructions (see Table 7–1 on page
7-4)
Auxiliary register and data page pointer instructions (see Table 7–2 on
page 7-7)
TREG, PREG, and multiply instructions (see Table 7–3 on page 7-7)
Branch instructions (see Table 7–4 on page 7-8)
Control instructions (see Table 7–5 on page 7-9)
I/O and memory operations (see Table 7–6 on page 7-10)
Within each table, the instructions are arranged alphabetically. The number of
words that an instruction occupies in program memory is specified in column
three of each table; the number of cycles that an instruction requires to execute
is in column four. All instructions are assumed to be executed from internal
program memory (RAM) and internal data dual-access memory. The cycle
timings are for single-instruction execution, not for repeat mode. Additional
information about each instruction is presented in the individual instruction
descriptions in Section 7.2.
For your reference, here are definitions of the symbols used in these six sum-
mary tables:
ACC The accumulator
AR Auxiliary register
ARX A 3-bit value used in the LAR and SAR instructions to desig-
nate which auxiliary register will be loaded (LAR) or have its
contents stored (SAR)
BITX A 4-bit value (called the bit code) that determines which bit of
a designated data memory value will be tested by the BIT
instruction
CM A 2-bit value. The CMPR instruction performs a comparison
specified by the value of CM:
If CM = 00, test whether current AR = AR0
If CM = 01, test whether current AR < AR0
If CM = 10, test whether current AR > AR0
If CM = 11, test whether current AR ≠ AR0