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Controlling and Resetting the Port
10-11
Asynchronous Serial Port
Bit 11 THRE — Transmit register (ADTR) empty indicator. THRE is set to 1
when the contents of the transmit register (ADTR) are transferred to the
transmit shift register (AXSR). THRE is reset to 0 by the loading of the trans-
mit register with a new character. A device reset sets THRE to 1.
The emptying of the ADTR also generates an interrupt (TXRXINT).
THRE = 0 The transmit register is not empty. Port operation is normal.
THRE = 1 The transmit register is empty, indicating that it is ready to be
loaded with a new character.
Bit 10 FE — Framing error indicator. FE indicates whether a valid stop bit has
been detected during reception. Clear the FE bit to 0 by writing a 1 to it. It
is also cleared to 0 on reset.
A framing error also generates an interrupt (TXRXINT).
FE = 0 No framing error is detected. Port operation is normal.
FE = 1 The character received did not have a valid (logic 1) stop bit.
Bit 9 OE — Receive register (ADTR) overrun indicator. OE indicates whether
an unread character has been overwritten. Clear the OE bit to 0 by writing
a 1 to it. It is also cleared to 0 on reset.
The occurrence of overrun also generates an interrupt (TXRXINT).
OE = 0 No overrun error is detected. The port is operating normally.
OE = 1 The last character in the ADTR was not read before the next
character overwrote it.
Bit 8 DR — Data ready indicator for the receiver. This bit indicates whether a
new character has been received in the ADTR. This bit is automatically
cleared to zero when the receive register (ADTR) is read or when the device
is reset.
The reception of a new character into the ADTR also generates an interrupt
(TXRXINT).
DR = 0 The receive register (ADTR) is empty.
DR = 1 A character has been completely received and should be read
from the receive register (ADTR).