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Index
Index-19
registers
(continued)
mapped to data page 0 4-8
mapped to I/O space
’C203/C204 4-24
’C209 11-9
accessing 4-25
quick reference A-1 to A-14
status registers ST0 and ST1 3-15
timer
control register (TCR)
’C203/C204 8-10
’C209 11-16
counter register (TIM) 8-12, F-23
divide-down register (TDDR)
’C203/C204 8-12
’C209 11-16
period register (PRD) 8-12, F-23
prescaler counter (PSC)
’C203/C204 8-11
’C209 11-15
wait-state generator control register (WSGR)
’C203/C204 8-15
’C209 11-17
repeat (RPT) instruction
description 7-146
introduction 5-14
repeat counter (RPTC) 5-14
repeating a single instruction 5-14
reset 5-33
at same time as HOLD operation 4-29
effects 5-33
introduction 5-27
priority
’C203/C204 5-16
’C209 11-10
vector location
’C203/C204 5-16
’C209 11-10
reset values of on-chip registers
mapped to data space 5-35, A-2
mapped to I/O space 5-35, A-2
status registers ST0 and ST1, A-2
RET instruction 7-142
RETC instruction 7-143
return instructions
conditional, overview 5-12
return conditionally from subroutine
(RETC) 7-143
return unconditionally from subroutine
(RET) 7-142
unconditional, overview 5-9
RFNE bit 9-9
RIM bit 10-8
RINT bit
in interrupt flag register (IFR) 5-22
in interrupt mask register (IMR) 5-23
RINT interrupt
definition F-19
flag bit 5-22
mask bit 5-23
priority 5-16
vector location 5-16
ROL instruction 7-144
ROM, customized D-1 to D-3
ROM (on-chip)
configuration
’C204 4-36
’C209 11-7
introduction 2-8
ROM codes, submitting to Texas Instru-
ments D-1 to D-3
ROR instruction 7-145
RPT instruction 7-146
RPTC (repeat counter), 5-14
RRST bit 9-10
RS
(reset)
at same time as HOLD operation 4-29
effects 5-33
introduction 5-27
priority
’C203/C204 5-16
’C209 11-10
vector location
’C203/C204 5-16
’C209 11-10
RSR (synchronous serial port receive shift regis-
ter) 9-5
run/stop operation E-10
RUNB, debugger command E-20, E-21, E-22,
E-23, E-24
RUNB_ENABLE, input E-22
RX pin 10-4