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Index-11
INT1
interrupt
’C203/C204
flag bit (HOLD/INT1) 5-22
mask bit (HOLD/INT1) 5-24
priority 5-16
vector location 5-16
’C209
flag bit 11-12
mask bit 11-13
priority 11-10
vector location 11-10
INT2 bit (’C209)
in interrupt flag register (IFR) 11-12
in interrupt mask register (IMR) 11-13
INT2
interrupt
’C203/C204
flag bits
FINT2 5-26
INT2/INT3 5-22
masking/unmasking in ICR 5-27
masking/unmasking in IMR 5-23
priority 5-16
vector location 5-16
’C209
flag bit 11-12
mask bit 11-13
priority 11-10
vector location 11-10
INT2/INT3 bit
in interrupt flag register (IFR) 5-22
in interrupt mask register (IMR) 5-23
INT20–INT31 (interrupts), vector locations
’C203/C204 5-17
’C209 11-11
INT3 bit (’C209)
in interrupt flag register (IFR) 11-12
in interrupt mask register (IMR) 11-13
INT3
interrupt
’C203/C204
flag bits
FINT3 5-26
INT2/INT3 5-22
masking/unmasking in ICR 5-26
masking/unmasking in IMR 5-23
priority 5-16
vector location 5-16
INT3 interrupt
(continued)
’C209
flag bit 11-12
mask bit 11-13
priority 11-10
vector location 11-10
INT8–INT16 (interrupts), vector locations
’C203/C204 5-16 to 5-17
’C209 11-10
interfacing
to external global data memory 4-12
to external I/O space 4-25
to external local data memory 4-9
to external program memory 4-5
internal oscillator, using (diagram) 8-4
interrupt 5-15 to 5-32
definitions 5-15, F-12
hardware interrupt
definition 5-15
priorities
’C203/C204 5-16
’C209 11-10
interrupt mode bit (INTM) 3-16
use in enabling/disabling maskable inter-
rupts 5-19
interrupt service routines (ISRs) 5-29 to 5-30
ISRs within ISRs 5-30
saving and restoring context 5-29 to 5-30
latency 5-30 to 5-36
after execution of RET 5-32
during execution of CLRC INTM 5-31
minimum latency 5-30
maskable interrupt 5-18 to 5-20
acknowledgement conditions 5-19
definition 5-15
enabling/disabling with INTM bit 5-19
flag bits in ICR 5-24
flag bits in IFR 5-20
flow chart of operation 5-20
flow chart of requesting INT2
and INT3 5-18
interrupt mode bit (INTM) 3-16
masking/unmasking in ICR 5-24 to 5-38
masking/unmasking in IMR 5-22 to 5-38
nonmaskable interrupt 5-27 to 5-29
definition 5-15
flow chart of operation 5-29
hardware-initiated 5-27
software-initiated 5-27
operation (three phases) 5-15
pending interrupt (IFR flag set) 5-20 to 5-22