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TMS320C2xx Generation
1-5
Introduction
1.2 TMS320C2xx Generation
Texas Instruments uses static CMOS integrated-circuit technology to fabricate
the TMS320C2xx DSPs. The architectural design of the ’C2xx is based on that
of the ’C5x. The operational flexibility and speed of the ’C2xx and ’C5x are a
result of an advanced, modified Harvard architecture (which has separate
buses for program and data memory), a multilevel pipeline, on-chip peripher-
als, on-chip memory, and a highly specialized instruction set. The ’C2xx per-
forms up to 40 MIPS (million instructions per second).
The ’C2xx generation offers the following benefits:
Enhanced TMS320 architectural design for increased performance and
versatility
Modular architectural design for fast development of additional spin-off
devices
Advanced IC processing technology for increased performance
Fast and easy performance upgrades for ’C1x and ’C2x source code,
which is upward compatible with ’C2xx source code
Enhanced instruction set for faster algorithms and for optimized high-level
language operation
New static design techniques for minimizing power consumption
Table 1–2 provides an overview of the basic features of the ’C2xx DSPs.
Table 1–2. ’C2xx Generation Summary
On-Chip Memory Serial Ports
Device
Cycle Time
(ns)
RAM ROM Flash Synch. Asynch. Timers Package
TMS320C203
25/35/50 544 1 1 1 100 TQFP
†
TMS320C204 25/35/50 544 4K 1 1 1 100 TQFP
†
TMS320F206 25/35/50 4.5K 32K 1 1 1 100 TQFP
†
TMS320C209 35/50 4.5K 4K – – 1 80 TQFP
†
†
TQFP = Thin quad flat pack