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F-18
program control logic: Logic circuitry that decodes instructions, manages
the pipeline, stores status of operations, and decodes conditional opera-
tions.
program counter (PC): A register that indicates the location of the next
instruction to be executed.
program read bus (PRDB): A 16-bit internal bus that carries instruction
code and immediate operands, as well as table information, from pro-
gram memory to the CPU.
PS
:
Program select pin
. The ’C2xx asserts PS to indicate an access to exter-
nal program memory.
PSC:
Timer prescaler counter
. Bits 9–6 of the timer control register (TCR);
specifies the prescale count for the on-chip timer.
PSLWS:
Lower program-space wait-state bits.
A value in the wait-state gen-
erator control register (WSGR) that determines the number of wait states
applied to reads from and writes to off-chip lower program space (ad-
dresses 0000h–7FFFh). PSLWS is not available on the ’C209; instead,
see
PSWS
. On other ’C2xx devices, PSLWS is bits 2–0 of the WSGR.
See also
PSUWS
.
PSUWS:
Upper program-space wait-state bits.
A value in the wait-state gen-
erator control register (WSGR) that determines the number of wait states
applied to reads from and writes to off-chip upper program space (ad-
dresses 8000h–FFFFh). PSUWS is not available on the ’C209; instead,
see
PSWS
. On other ’C2xx devices, PSUWS is bits 5–3 of the WSGR.
See also
PSLWS
.
PSWS:
Program-space wait-state bit.
Bit 0 of the ’C209 wait-state generator
control register (WSGR). PSWS determines the number of wait states
applied to reads from off-chip program memory space.
R
RAMEN:
RAM enable pin
. This pin enables or disables on-chip single-ac-
cess RAM.
RD
:
Read select pin
. The ’C2xx asserts RD to request a read from external
program, data, or I/O space. RD
can be connected directly to the output
enable pin of an external device.
READY:
External device ready pin
. Used to create wait states externally.
When this pin is driven low, the ’C2xx waits one CPU cycle and then tests
READY again. After READY is driven low, the ’C2xx does not continue
processing until READY is driven high.
Glossary