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SUBT
Subtract From Accumulator With Shift Specified by TREG
7-184
Syntax SUBT
dma
Direct addressing
SUBT
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
SUBT
dma
1514131211109876543210
0
11001110 dma
SUBT
ind
[, AR
n
]
1514131211109876543210
0
11001111 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(ACC) – [(data-memory address) 2
(TREG(3:0))
] → (ACC)
If SXM = 1
Then (data-memory address) is sign-extended.
If SXM = 0
Then (data-memory address) is not sign-extended.
Status Bits
Affected by Affects
OVM and SXM OV and C
Description The data-memory value is left shifted and subtracted from the accumulator.
The left shift is defined by the four LSBs of TREG, resulting in shift options from
0 to 15 bits. The result replaces the accumulator contents. Sign extension on
the data-memory value is controlled by the SXM status bit.
The carry bit is cleared (C = 0) if the result of the subtraction generates a bor-
row and is set (C = 1) if it does not generate a borrow.
Words 1
Opcode