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Central Arithmetic Logic Section
3-9
Central Processing Unit
3.3.1 Central Arithmetic Logic Unit (CALU)
The central arithmetic logic unit (CALU), implements a wide range of arithme-
tic and logic functions, most of which execute in a single clock cycle. These
functions can be grouped into four categories:
16-bit addition
16-bit subtraction
Boolean logic operations
Bit testing, shifting, and rotating.
Because the CALU can perform Boolean operations, you can perform bit ma-
nipulation. For bit shifting and rotating, the CALU uses the accumulator. The
CALU is referred to as central because there is an independent arithmetic unit,
the auxiliary register arithmetic unit (ARAU), which is described in Section 3.4.
A description of the inputs, the output, and an associated status bit of the CALU
follows.
Inputs. The CALU has two inputs (see again Figure 3–6):
One input is always provided by the 32-bit accumulator.
The other input is provided by one of the following:
The product-scaling shifter (see subsection 3.2.2)
The input data-scaling shifter (see Section 3.1)
Output. Once the CALU performs an operation, it transfers the result to the
32-bit accumulator, which is capable of performing bit shifts of its contents. The
output of the accumulator is connected to the 32-bit output data-scaling shifter.
Through the output shifter, the accumulator’s upper and lower 16-bit words
can be individually shifted and stored to data memory.
Sign-extension mode bit. For many but not all instructions, the sign-exten-
sion mode bit (SXM), bit 10 of status register ST1, determines whether the
CALU uses sign extension during its calculations. If SXM = 0, sign extension
is suppressed. If SXM = 1, sign extension is enabled.
3.3.2 Accumulator
Once the CALU performs an operation, it transfers the result to the 32-bit accu-
mulator, which can then perform single-bit shifts or rotations on its contents.
Each of the accumulator’s upper and lower 16-bit words can be passed to the
output data-scaling shifter, where it can be shifted, and then stored in data
memory. Status bits and branch instructions associated with the accumulator
are discussed directly below.