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Timer
8-8
8.4 Timer
The ’C2xx features an on-chip timer with a 4-bit prescaler. This timer is a down
counter that can be stopped, restarted, reset, or disabled by specific status
bits. You can use the timer to generate periodic CPU interrupts.
Figure 8–4 shows a functional block diagram of the timer. There is a 16-bit
main counter (TIM) and a 4-bit prescaler counter (PSC). The TIM is reloaded
from the period register PRD. The PSC is reloaded from the period register
TDDR.
Figure 8–4. Timer Functional Block Diagram
PRD
TIM
Borrow
TDDR
PSC
Borrow
SRESET
TRB
CLKOUT1
TSS
TINT
TOUT
Each time a counter decrements to zero, a borrow is generated on the next
CLKOUT1 cycle, and the counter is reloaded with the contents of its corre-
sponding period register. The contents of the PRD are loaded into the TIM
when the TIM decrements to 0 or when a 1 is written to the timer reload bit
(TRB) in the timer control register (TCR). Similarly, the PSC is loaded with the
value in the TDDR when the PSC decrements to 0 or when a 1 is written to
TRB.
When the TIM decrements to 0, it generates a borrow pulse that has a duration
equal to that of a CLKOUT1 cycle (t
c(C)
). This pulse is sent to:
The external timer output (TOUT) pin
The CPU, as a timer interrupt (TINT) signal