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LSB:
Least significant bit.
The lowest order bit in a word. When used in plural
form (LSBs), refers to a specified number of low-order bits, beginning
with the lowest order bit and counting to the left. For example, the four
LSBs of a 16-bit value are bits 0 through 3. See also
MSB
.
M
machine cycle: See
CPU cycle
.
maskable interrupt: A hardware interrupt that can be enabled or disabled
through software. See also
nonmaskable interrupt
.
master clock output signal: See
CLKOUT1
.
master phase: See
logic phase
.
MCM bit: See
clock mode bit (MCM)
.
memory-mapped register: One of the on-chip registers mapped to ad-
dresses in data memory. See also
I/O-mapped register
.
microcomputer mode: A mode in which the on-chip ROM or flash memory
is enabled. This mode is selected with the MP/MC
pin. See also
MP/MC
pin
;
microprocessor mode
.
microprocessor mode: A mode in which the on-chip ROM or flash memory
is disabled. This mode is selected with the MP/MC
pin. See also
MP/MC
pin
;
microcomputer mode
.
micro stack (MSTACK): A register used for temporary storage of the pro-
gram counter (PC) value when an instruction needs to use the PC to ad-
dress a second operand.
MIPS: Million instructions per second.
MODE bit: Bit 4 of the interrupt control register (ICR); determines whether
the HOLD
/INT1 pin is only negative-edge sensitive or both negative- and
positive-edge sensitive.
MP/MC
pin: A pin that indicates whether the processor is operating in micro-
processor mode or microcomputer mode. MP/MC
high selects micropro-
cessor mode; MP/MC
low selects microcomputer mode.
MSB:
Most significant bit.
The highest order bit in a word. When used in plu-
ral form (MSBs), refers to a specified number of high-order bits, begin-
ning with the highest order bit and counting to the right. For example, the
eight MSBs of a 16-bit value are bits 15 through 8. See also
LSB
.
GlossaryGlossary