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Components and Basic Operation
10-5
Asynchronous Serial Port
I/O status register (IOSR). Bits in the IOSR indicate detection of the in-
coming baud rate, various error conditions, the status of data transfers,
detection of a break on the RX pin, the status of pins IO3–IO0, and detec-
tion of changes on pins IO3–IO0. The IOSR is at address FFF6h in I/O
space. For detailed descriptions of the bits in the IOSR, see subsection
10.3.2.
Baud-rate divisor register (BRD). The 16-bit value in the BRD is a divisor
used to determine the baud rate for data transfers. BRD (at address
FFF7h in I/O space) is either loaded by software or is loaded by the port
when the automatic baud-rate detection logic is enabled and samples the
incoming baud rate. Subsection 10.3.3 describes how to determine the
BRD value that will produce the desired baud rate.
Two other registers (not accessible to a programmer) control transfers be-
tween the ADTR and the pins:
Asynchronous serial port transmit shift register (AXSR). During
transmissions, each data character is transferred from the ADTR to the
AXSR. The AXSR then shifts the character out (LSB first) through the TX
pin.
Asynchronous serial port receive shift register (ARSR). During recep-
tions, each data character is accepted, one bit at a time (LSB first), at the
RX pin and shifted into the ARSR. The ARSR then transfers the character
to the ADTR.
10.2.4 Interrupts
The asynchronous serial port has one hardware interrupt (TXRXINT), which
can be generated by various events (described in subsection 10.3.6).
TXRXINT leads the CPU to interrupt vector location 000Ch in program
memory. The branch at that location should lead to an interrupt service routine
that identifies the cause of the interrupt and then acts accordingly. TXRXINT
has a priority level of 9 (1 being highest).
TXRXINT is a maskable interrupt controlled by the interrupt mask register
(IMR) and interrupt flag register (IFR).
Note:
To avoid a double interrupt from the ASP, clear the IFR bit (TXRXINT) in the
corresponding interrupt service routine, just before returning from the rou-
tine.