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’C2xx Bus Structure
2-3
Architectural Overview
2.1 ’C2xx Bus Structure
Figure 2–2 shows a block diagram of the ’C2xx bus structure. The ’C2xx inter-
nal architecture is built around six 16-bit buses:
PAB. The
program address bus
provides addresses for both reads from
and writes to program memory.
DRAB. The
data-read address bus
provides addresses for reads from
data memory.
DWAB. The
data-write address bus
provides addresses for writes to data
memory.
PRDB. The
program read bus
carries instruction code and immediate
operands, as well as table information, from program memory to the CPU.
DRDB. The
data read bus
carries data from data memory to the central
arithmetic logic unit (CALU) and the auxiliary register arithmetic unit
(ARAU).
DWEB. The
data write bus
carries data to both program memory and data
memory.
Having separate address buses for data reads (DRAB) and data writes
(DWAB) allows the CPU to read and write in the same machine cycle.
Separate program and data spaces allow simultaneous access to program
instructions and data. For example, while data is multiplied, a previous product
can be added to the accumulator, and, at the same time, a new address can
be generated. Such parallelism supports a set of arithmetic, logic, and bit-ma-
nipulation operations that can all be performed in a single machine cycle. In
addition, the ’C2xx includes control mechanisms to manage interrupts, re-
peated operations, and function/subroutine calls.
All ’C2xx devices share the same CPU and bus structure; however, each de-
vice has different on-chip memory configurations and on-chip peripherals.