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Add to Accumulator With Shift Specified by TREG
ADDT
7-31
Assembly Language Instructions
Syntax ADDT
dma
Direct addressing
ADDT
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
ADDT
dma
1514131211109876543210
0
11000110 dma
ADDT
ind
[, AR
n
]
1514131211109876543210
0
11000111 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(ACC) + [(data-memory address) 2
(TREG(3:0))
] → (ACC)
Status Bits
Affected by Affects
SXM or OVM C and OV
Description The data-memory value is left shifted and added to the accumulator, and the
result replaces the accumulator contents. The left shift is defined by the four
LSBs of the TREG, resulting in shift options from 0 to 15 bits. Sign extension
on the data-memory value is controlled by SXM. The carry bit (C) is set when
a carry is generated out of the MSB of the accumulator; if no carry is generated,
the carry bit is cleared.
Words 1
Cycles for a Single ADDT Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2
†
1+p
External 1+d 1+d 1+d 2+d+p
†
If the operand and the code are in the same SARAM block.
Opcode
Cycles