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LACT
Load Accumulator With Shift Specified by TREG
7-78
Syntax LACT
dma
Direct addressing
LACT
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
LACT
dma
1514131211109876543210
0
11010110 dma
LACT
ind
[, AR
n
]
1514131211109876543210
0
11010111 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(data-memory address) × 2
(TREG(3:0))
→ ACC
If SXM = 1:
Then (data-memory address) is sign extended.
If SXM = 0:
Then (data-memory address) is not sign extended.
Status Bits
Affected by
SXM
Description The LACT instruction loads the accumulator with a data-memory value that
has been left shifted. The left shift is specified by the four LSBs of the TREG,
resulting in shift options from 0 to 15 bits. Using the four LSBs of the TREG as
a shift code provides a dynamic shift mechanism. During shifting, the high-or-
der bits are sign extended if SXM = 1 and zeroed if SXM = 0.
LACT may be used to denormalize a floating-point number if the actual expo-
nent is placed in the four LSBs of the TREG register and the mantissa is refer-
enced by the data-memory address. This method of denormalization can be
used only when the magnitude of the exponent is four bits or less.
Words 1
Opcode