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Indirect Addressing Mode
6-14
Table 6–3. Field Bits and Notation for Indirect Addressing
Instruction Opcode Bits
15 – 8 7 6 5 4 3 2 1 0 Operand(s) Operation
← 8 MSBs → 10000←NAR→ * No manipulation of current AR
← 8 MSBs → 10001←NAR→ *,AR
n
NAR → ARP
← 8 MSBs → 10010←NAR→ *– current AR – 1 → current AR
← 8 MSBs → 10011←NAR→ *–,AR
n
current AR – 1 → current AR
NAR → ARP
← 8 MSBs → 10100←NAR→ *+ current AR + 1 → current AR
← 8 MSBs → 10101←NAR→ *+,AR
n
current AR + 1 → current AR
NAR → ARP
← 8 MSBs → 11000←NAR→ *BR0– current AR –
rc
AR0 → current AR †
← 8 MSBs → 11001←NAR→ *BR0–,AR
n
current AR –
rc
AR0 → current AR
NAR → ARP
†
← 8 MSBs → 11010←NAR→ *0– current AR – AR0 → current AR
← 8 MSBs → 11011←NAR→ *0–,AR
n
current AR – AR0 → current AR
NAR → ARP
← 8 MSBs → 11100←NAR→ *0+ current AR + AR0 → current AR
← 8 MSBs → 11101←NAR→ *0+,AR
n
current AR + AR0 → current AR
NAR → ARP
← 8 MSBs → 11110←NAR→ *BR0+ current AR +
rc
AR0 → current AR †
← 8 MSBs → 11111←NAR→ *BR0+,AR
n
current AR +
rc
AR0 → current AR
NAR → ARP
†
†
Bit-reversed addressing mode
Legend:
rc
Reverse carry propagation
NAR Next AR
n
0, 1, 2, ..., or 7
8 MSBs Eight bits determined by instruction type and (sometimes) shift information
→ Is loaded into