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Test Bit Specified by TREG
BITT
7-47
Assembly Language Instructions
Syntax BITT
dma
Direct addressing
BITT
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
BITT
dma
1514131211109876543210
0
11011110 dma
BITT
ind
[, AR
n
]
1514131211109876543210
0
11011111 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(data bit number (15 –TREG(3:0))) → TC
Status Bits
Affects
TC
Description The BITT instruction copies the specified bit of the data-memory value to the
TC bit of status register ST1. Note that the BITT, CMPR, LST #1, and NORM
instructions also affect the TC bit in status register ST1. The bit number is spe-
cified by a bit code value contained in the four LSBs of the TREG, as shown
in Figure 7–2.
Figure 7–2. Bit Numbers and Their Corresponding Bit Codes for BITT Instruction
Bit code (in 4 LSBs of
TREG)
0123456789101112131415
Bit number 15 14 13 12 11 10 9876543210
MSB
Data-memory value
LSB
Words 1
Opcode