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Reset Operation
5-35
Program Control
Table 5–6. Reset Values of On-Chip Registers Mapped to Data Space
Name Data-Memory Address Reset Value Description
IMR 0004h 0000h Interrupt mask register
GREG 0005h 0000h Interrupt control register
IFR
0006h 0000h Synchronous data transmit and receive register
Table 5–7. Reset Values of On-Chip Registers Mapped to I/O Space
I/O Address
Name ’C209 Other ’C2xx Reset Value Description
CLK
– FFE8h 0000h CLKOUT1-pin control (CLK) register
ICR – FFECh 0000h Interrupt control register
SDTR – FFF0h xxxxh Synchronous data transmit and receive register
SSPCR – FFF1h 0030h Synchronous serial port control register
ADTR – FFF4h xxxxh Asynchronous data transmit and receive register
ASPCR – FFF5h 0000h Asynchronous serial port control register
IOSR – FFF6h 18xxh I/O status register
BRD – FFF7h 0001h Baud-rate divisor register
TCR FFFCh FFF8h 0000h Timer control register
PRD FFFDh FFF9h FFFFh Timer period register
TIM FFFEh FFFAh FFFFh Timer counter register
WSGR FFFFh FFFCh 0FFFh Wait-state generator control register
Note: An x in an address represents four bits that are either not affected by reset or dependent on pin levels at reset.