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Index-3
asynchronous serial port
(continued)
baud-rate detection logic
detecting
A
or
a
character (ADC bit) 10-10
enabling/disabling (CAD bit) 10-8
block diagram 10-3
components 10-3
configuration 10-7
delta interrupts 10-17
enabling/disabling (DIM bit) 10-8
emulation modes (FREE and SOFT bits) 10-7
features 10-1
interrupts (TXRXINTs)
flag bit (TXRXINT) 5-21
introduction 10-5
mask bit in IMR (TXRXINT) 5-23
mask bits in ASPCR (DIM, TIM, RIM) 10-8
priority 5-16
three types 10-17
vector location 5-16
introduction 2-12
overrun in receiver, detecting (OE bit) 10-11
overview 10-2
receive interrupts 10-17
enabling/disabling (RIM bit) 10-8
receive pin (RX)
definition 10-4
detecting break on (BI bit) 10-10
receiver operation 10-20
reset conditions 5-34
resetting (URST bit) 10-7
signals 10-3
data 10-3
handshake 10-3
stop bit(s)
detecting invalid (FE bit) 10-11
setting number of (STB bit) 10-8
transmit interrupts 10-17
enabling/disabling (TIM bit) 10-8
transmit pin (TX)
definition 10-4
output level between transmissions (SETBRK
bit) 10-8
transmitter operation 10-19
asynchronous serial port registers
baud-rate divisor register (BRD) 10-13
control register (ASPCR) 10-7
configuring pins IO0–IO3 as inputs/out-
puts 10-15
quick reference A-13
asynchronous serial port registers
(continued)
I/O status register (IOSR)
description 10-10
quick reference A-13
introduction 10-4
receive register (ADTR)
detecting overrun in (OE bit) 10-11
detecting when empty (DR bit) 10-11
receive shift register (ARSR) 10-5
receive/transmit register (ADTR) 10-4
transmit register (ADTR)
detecting when empty (THRE bit) 10-11
detecting when it and AXSR are empty (TEMT
bit) 10-10
transmit shift register (AXSR) 10-5
detecting when it and ADTR are empty (TEMT
bit) 10-10
transmit/receive register (ADTR) 10-4
automatic baud-rate detection 10-14
auxiliary register arithmetic unit (ARAU), descrip-
tion 3-12
auxiliary register instructions
add short immediate value to current auxiliary
register (ADRK) 7-33
branch if current auxiliary register not zero
(BANZ) 7-41
compare current auxiliary register with AR0
(CMPR) 7-65
load specified auxiliary register (LAR) 7-80
modify auxiliary register pointer (MAR) 7-111
modify current auxiliary register (MAR) 7-111
store specified auxiliary register (SAR) 7-152
subtract short immediate value from current aux-
iliary register (SBRK) 7-154
auxiliary register pointer (ARP) 3-16, F-2
auxiliary register pointer buffer (ARB) 3-16, F-2
auxiliary register update (ARU) code 6-13
auxiliary registers (AR0–AR7)
block diagram 3-12
current auxiliary register 6-9
role in indirect addressing 6-9 to 6-18
update code (ARU) 6-13
description 3-12 to 3-14
general uses for 3-14
instructions that modify content 6-17
next auxiliary register 6-11
used in indirect addressing 3-12
AVIS bit 11-17
AXSR (asynchronous serial port transmit shift regis-
ter) 10-5