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SACH instruction 7-148
SACL instruction 7-150
SAR instruction 7-152
SARAM (single-access RAM)
configuration 11-7
definition F-20
description 2-8
SBRK instruction 7-154
scaling shifters
input shifter 3-3
introduction 2-5
output shifter 3-11
product shifter 3-6
product shift modes 3-7
scan path linkers E-16
secondary JTAG scan chain to an SPL E-17
suggested timings E-22
usage E-16
scan paths, TBC emulation connections for JTAG
scan paths E-25
scanning logic overview 2-13
SDTR (synchronous serial port transmit and receive
register) 9-5
using to access FIFO buffers 9-15
serial ports
See also
synchronous serial port; asynchronous
serial port
available on TMS320C2xx devices 2-12
introduction 2-12
reset conditions 5-34
serial-scan emulation capability 2-13
SETBRK bit 10-8
SETC instruction 7-155
SFL instruction 7-157
SFR instruction 7-158
shifters
input shifter 3-3
introduction 2-5
output shifter 3-11
product shifter 3-6
product shift modes 3-7
short immediate addressing 6-2
signal descriptions, 14-pin header E-3
signals
buffered E-10
buffering for emulator connections E-10 to E-13
description, 14-pin header E-3
timing E-6
sign-extension mode bit (SXM)
definition 3-17
effect on CALU (central arithmetic logic
unit) 3-9
effect on input shifter 3-4
single-access RAM (SARAM)
configuration 11-7
definition F-20
description 2-8
single-access RAM enable pin (RAMEN)
definition 4-4
use in configuring memory 11-7
slave devices E-4
SOFT bit
asynchronous serial port 10-7
synchronous serial port 9-8
timer 8-11
software interrupts
definition 5-15
instructions 5-27
SPAC instruction 7-160
SPH instruction 7-161
SPL instruction 7-163
SPLK instruction 7-165
SPM instruction 7-167
SQRA instruction 7-168
SQRS instruction 7-170
SSPCR (synchronous serial port control regis-
ter) 9-8
quick reference A-12
SST instruction 7-172
ST0.
See
status registers ST0 and ST1
ST1.
See
status registers ST0 and ST1
stack 5-4
managing nested interrupt service routines 5-30
pop top of stack to data memory (POPD instruc-
tion) 7-137
pop top of stack to low accumulator bits (POP
instruction) 7-135
push data memory value onto stack (PSHD
instruction) 7-139
push low accumulator bits onto stack (PUSH
instruction) 7-141