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Transmitter Operation
9-20
9.5.3 Continuous Mode Transmission With Internal Frame Sync (FSM = 0, TXM = 1)
Use continuous mode transmission with internal frame sync to transfer long
packets at maximum packet frequency while using an internal frame sync gen-
erator. Place the transmitter in continuous mode with internal frame sync by
setting the FSM bit to 0 and the TXM bit to 1.
In continuous mode, frame sync pulses are not necessary after the initial pulse
for consecutive packet transfers. A frame sync is generated only for the first
transmission. As long as the FIFO buffer has new values to transmit, the mode
continues. Transmission halts when the buffer empties. If SDTR is written to
after the halt, the device starts a new continuous mode transmission.
This mode of operation offers several features:
A write to the SDTR begins the transmission.
A one-clock-cycle frame-sync pulse is generated internally at the begin-
ning of the transmission.
As long as data is maintained in the transmit FIFO buffer, the mode
continues.
Failure to update the FIFO buffer causes the process to end.
Generally, the transmit clock and the receive clock have the same source. This
allows each bit to be transmitted from another device on a rising edge of the
clock signal and received by the ’C2xx on the next falling edge of the clock sig-
nal.
As illustrated by Figure 9–6, in this mode, the port operates as follows:
1) The transfer is initiated by a write to the SDTR.
2) The write to the SDTR causes a frame sync pulse to be generated on the
next rising edge of CLKX. The frame sync pulse remains high for one clock
cycle.
3) On the next rising edge of CLKX after FSX goes high, the XSR is loaded
with the earliest-written value from the transmit FIFO buffer, and the frame
sync pulse goes low. Additionally, the first data bit (MSB first) is driven on
the DX pin. If the FIFO buffer becomes empty during this operation, then
it generates a XINT to request more data.
4) The rest of the bits are then shifted out. Each new bit is transmitted at the
rising edge of CLKX.
5) Once the entire word in the XSR is shifted out, the next word is loaded in
and the first bit of the word is placed on the DX pin. Then, the process re-
peats beginning with step four. If a new word is not in the transmit FIFO
buffer, the process ends.