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LACC
Load Accumulator With Shift
7-72
Syntax LACC
dma
[,
shift
] Direct addressing
LACC
dma,
16 Direct with left shift of 16
LACC
ind
[,
shift
[, AR
n
]] Indirect addressing
LACC
ind
,
16[, AR
n
] Indirect with left shift of 16
LACC #
lk
[,
shift
] Long immediate addressing
Operands dma: 7 LSBs of the data-memory address
shift: Left shift value from 0 to 15 (defaults to 0)
n: Value from 0 to 7 designating the next auxiliary register
lk: 16-bit long immediate value
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
LACC
dma
[,
shift
]
1514131211109876543210
0
001 shift 0 dma
LACC
dma
,
16
1514131211109876543210
0
11010100 dma
LACC
ind
[,
shift
[, AR
n
]]
1514131211109876543210
0
001 shift 1 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
LACC
ind
, 16[, AR
n
]
1514131211109876543210
0
11010101 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
LACC #
lk
[,
shift
]
1514131211109876543210
1
01111111000 shift
lk
Opcode