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ZALR
Zero Low Accumulator and Load High Accumulator With Rounding
7-196
Syntax ZALR
dma
Direct addressing
ZALR
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
ZALR
dma
1514131211109876543210
0
11010000 dma
ZALR
ind
[, AR
n
]
1514131211109876543210
0
11010001 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
(data-memory address) → ACC(31:16)
8000h → ACC(15:0)
Status Bits None
Description To load a data-memory value into the high-order half of the accumulator, the
ZALR instruction rounds the value by adding 1/2 LSB; that is, the 15 low bits
(bits 14–0) of the accumulator are cleared to 0, and bit 15 of the accumulator
is set to 1.
Words 1
Cycles for a Single ZALR Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2
†
1+p
External 1+d 1+d 1+d 2+d+p
†
If the operand and the code are in the same SARAM block
Opcode
Cycles