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Index-6
CMPR instruction 7-65
CNF (DARAM configuration bit) 3-16
code compatibility 1-6
codec, definition F-5
conditional instructions 5-10 to 5-13
conditional branch 5-11 to 5-13
conditional call 5-12 to 5-13
conditional return 5-12 to 5-13
conditions that may be tested 5-10
stabilization of conditions 5-11
using multiple conditions 5-10
configuration
memory
global data 4-11
RAM (dual-access)
’C203 4-33
’C204 4-36
’C209 11-8
RAM (single-access) 11-7
ROM
’C204 4-36
’C209 11-7
multiprocessor E-13
connector
14-pin header E-2
dimensions, mechanical E-14
DuPont E-2
continuous mode
error conditions 9-29
reception 9-25
transmission
with external frame sync 9-22
with internal frame sync 9-20
control instructions (summary) 7-9
CPU 3-1 to 3-18
accumulator 3-9
arithmetic logic section 3-8
auxiliary register arithmetic unit (ARAU) 3-12
block diagram (partial) 3-2
CALU (central arithmetic logic unit) 3-9
central arithmetic logic unit (CALU) 3-9
definition F-5
input scaling section/input shifter 3-3
key features 1-6
multiplication section 3-5
output shifter 3-11
overview 2-5
CPU
(continued)
product shifter 3-6
product shift modes 3-7
status registers ST0 and ST1 3-15
current auxiliary register 6-9
add short immediate value to (ADRK instruc-
tion) 7-33
branch if not zero (BANZ instruction) 7-41
compare with AR0 (CMPR instruction) 7-65
increment or decrement (MAR instruc-
tion) 7-111
role in indirect addressing 6-9 to 6-18
subtract short immediate value from (SBRK
instruction) 7-154
update code (ARU) 6-13
D
D0–D15 (external data bus)
definition 4-3, F-6
shown in figure 4-6, 4-10, 4-13, 4-15, 4-26
DARAM (dual-access RAM)
configuration
’C203 4-33
’C204 4-36
’C209 11-8
description 2-7
DARAM configuration bit (CNF) 3-16
data memory
address map
’C203 4-32
’C204 4-35
’C209 11-6
data page 0 4-8
caution about reserved addresses 4-33, 4-36,
11-7
configuration
RAM (dual-access)
’C203 4-33
’C204 4-36
’C209 11-8
RAM (single-access) 11-7
data page pointer (DP) 3-16
external interfacing
caution about proper timing 4-9
global 4-12
local 4-9
global 4-11
local 4-7
on-chip registers mapped to 4-8