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Index-15
next program address register (NPAR)
definition F-15
shown in figure 5-2
NMI
hardware interrupt
description 5-27
priority
’C203/C204 5-17
’C209 11-11
vector location
’C203/C204 5-17
’C209 11-11
NMI instruction 7-124
introduction 5-28
vector location
’C203/C204 5-17
’C209 11-11
nonmaskable interrupts 5-27
definition 5-15
flow chart of operation 5-29
hardware-initiated 5-27
software-initiated 5-27
NOP instruction 7-125
NORM instruction 7-126
NPAR (next program address register)
definition F-15
shown in figure 5-2
O
OE bit 10-11
off-chip (external) memory
’C203 4-32
’C204 4-35
’C209 11-6
on-chip generators
baud-rate generator 10-4
clock generator 8-4
’C209 clock options 11-14
wait-state generator 8-14
’C209 11-16
on-chip memory
advantages 4-2
flash, introduction 2-9
on-chip memory
(continued)
RAM (dual-access)
available
’C203 4-32
’C204 4-35
’C209 11-6
configuration
’C203 4-33
’C204 4-36
’C209 11-8
description 2-7
RAM (single-access)
available, ’C209 11-6
configuration 11-7
description 2-8
ROM
available
’C204 4-35
’C209 11-6
configuration
’C204 4-36
’C209 11-7
introduction 2-8
on-chip peripherals
asynchronous serial port 10-1 to 10-20
available types 1-7
clock generator 8-4 to 8-6
’C209 clock options 11-14 to 11-18
control of 8-2 to 8-3
general-purpose I/O pins 8-17 to 8-20
overview 2-11
register locations and reset values 8-2
reset conditions 5-34, 8-2
synchronous serial port 9-1 to 9-30
timer 8-8 to 8-13
wait-state generator 8-14 to 8-16
’C209 11-16 to 11-18
on-chip registers mapped to data space
addresses and reset values A-2
quick reference figures A-4
on-chip registers mapped to I/O space
addresses and reset values A-2
quick reference figures A-4
on-chip ROM D-1
opcode format
direct addressing 6-5
immediate addressing 6-2
indirect addressing 6-12
OR instruction 7-129
oscillator 8-4