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F-22
status registers ST0 and ST1: Two 16-bit registers that contain bits for de-
termining processor modes, addressing pointer values, and indicating
various processor conditions and arithmetic logic results. These regis-
ters can be stored into and loaded from data memory, allowing the status
of the machine to be saved and restored for subroutines.
STB bit:
Stop bit selector
. Bit 6 of the asynchronous serial port control regis-
ter (ASPCR); selects the number of stop bits (one or two) used in trans-
mission and reception.
stop bit: Every 8-bit data value transmitted or received by the asynchronous
serial port must be followed by one or two stop bits, each a logic 1 pulse.
The number of stop bits required depends on the STB bit of the ASPCR.
STRB
:
External access active strobe
. The ’C2xx asserts STRB during ac-
cesses to external program, data, or I/O space.
SXM bit: See
sign-extension mode bit (SXM).
T
TC bit:
Test/control flag bit
. Bit 11 of status register ST1; stores the results
of test operations done in the central arithmetic logic unit (CALU) or the
auxiliary register arithmetic unit (ARAU). The TC bit can be tested by
conditional instructions.
TCOMP:
Transmission complete bit
. Bit 13 of the synchronous serial port
control register (SSPCR); indicates when all data in the transmit FIFO
buffer of the synchronous serial port has been transmitted.
TCR:
Timer control register.
A 16-bit register that controls the operation of
the on-chip timer.
TDDR: See
timer divide-down register (TDDR)
.
temporary register (TREG): A 16-bit register that holds one of the oper-
ands for a multiply operation; the dynamic shift count for the LACT,
ADDT, and SUBT instructions; or the dynamic bit position for the BITT
instruction.
TEMT bit:
Transmit empty indicator
. Bit 12 of the I/O status register (IOSR);
indicates whether the transmit register (ADTR) and/or the transmit shift
register (AXSR) of the asynchronous serial port are full or empty.
THRE bit:
Transmit register empty indicator
. Bit 11 of the I/O status register
(IOSR); indicates when the contents of the transmit register (ADTR) are
transferred to the transmit shift register (AXSR).
Glossary