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Store High PREG
SPH
7-161
Assembly Language Instructions
Syntax SPH
dma
Direct addressing
SPH
ind
[, AR
n
] Indirect addressing
Operands dma: 7 LSBs of the data-memory address
n: Value from 0 to 7 designating the next auxiliary register
ind: Select one of the following seven options:
* *+ *– *0+ *0– *BR0+ *BR0–
SPH
dma
1514131211109876543210
1
00011010 dma
SPH
ind
[, AR
n
]
1514131211109876543210
1
00011011 ARU N NAR
Note: ARU, N, and NAR are defined in Section 6.3,
Indirect Addressing Mode
(page 6-9).
Execution Increment PC, then ...
16 MSBs of shifted (PREG) → data-memory address
Status Bits
Affected by
PM
Description The 16 high-order bits of the PREG, shifted as specified by the PM bits, are
stored in data memory. First, the 32-bit PREG value is copied into the product
shifter, where it is shifted as specified by the PM bits. If the right-shift-by-6
mode is selected, the high-order bits are sign extended and the low-order bits
are lost. If a left shift is selected, the high-order bits are lost and the low-order
bits are zero filled. If PM = 00, no shift occurs. Then the 16 MSBs of the shifted
value are stored in data memory. Neither the PREG value nor the accumulator
value is modified by this instruction.
Words 1
Cycles for a Single SPH Instruction
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2
†
1+p
External 2+d 2+d 2+d 4+d+p
†
If the operand and the code are in the same SARAM block
Opcode
Cycles