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Index-2
accumulator instructions
(continued)
store high byte of accumulator to data memory
(SACH) 7-148
store low byte of accumulator to data memory
(SACL) 7-150
subtract conditionally from accumulator
(SUBC) 7-180
subtract PREG from accumulator (SPAC) 7-160
subtract PREG from accumulator and load TREG
(LTS) 7-100
subtract PREG from accumulator and multiply
(MPYS) 7-118
subtract PREG from accumulator and square
specified value (SQRS) 7-170
subtract value and logical inversion of carry bit
from accumulator (SUBB) 7-178
subtract value from accumulator (SUB) 7-174
subtract value from accumulator with shift speci-
fied by TREG (SUBT) 7-184
subtract value from accumulator with sign exten-
sion suppressed (SUBS) 7-182
XOR accumulator with data value (XOR) 7-193
ADC bit 10-10
add.
See
accumulator instructions
ADD instruction 7-23
ADDC instruction 7-27
address generation
data memory
direct addressing 6-4
immediate addressing 6-2
indirect addressing 6-9
program memory 5-2
hardware 5-3
address maps
’C203 4-32
’C204 4-35
’C209 11-6
data page 0 4-8
address visibility mode (AVIS bit) 11-17
addressing, bit-reversed indexed 6-10, F-3
addressing modes
definition F-1
direct
description 6-4
examples 6-6
figure 6-5
opcode format 6-5 to 6-7
role of data page pointer (DP) 6-4
immediate 6-2
addressing modes
(continued)
indirect
description 6-9
effects on auxiliary register pointer
(ARP) 6-14 to 6-16
effects on current auxiliary regis-
ter 6-14 to 6-16
examples 6-15
modifying auxiliary register content 6-17
opcode format 6-12 to 6-14
operands 6-9
operation types 6-14 to 6-16
options 6-9
possible opcodes 6-14 to 6-16
overview 6-1
ADDS instruction 7-29
ADDT instruction 7-31
ADRK instruction 7-33
ADTR (asynchronous serial port transmit and re-
ceive register) 10-4
AND instruction 7-34
APAC instruction 7-37
applications, TMS320 devices 1-4
ARAU (auxiliary register arithmetic unit) 3-12
ARAU and related logic, block diagram 3-12
ARB (auxiliary register pointer buffer) 3-16
architecture of ’C2x
2-1 to 2-14
arithmetic instructions.
See
accumulator instruc-
tions; auxiliary register instructions
arithmetic logic unit, central (CALU) 3-9
ARP (auxiliary register pointer) 3-16
ARSR (asynchronous serial port receive shift regis-
ter) 10-5
ASPCR (asynchronous serial port control regis-
ter) 10-7
configuring pins IO0–IO3 as inputs/out-
puts 10-15
quick reference A-13
assembly language instructions.
See
instructions
asynchronous
reception 10-20
transmission 10-19
asynchronous serial port
See also
asynchronous serial port registers
basic operation 10-6
baud rates
common 10-14
setting 10-13